Datasheet

Section 26 Electrical Characteristics
Rev. 2.00 Sep. 28, 2009 Page 826 of 870
REJ09B0429-0200
t DEXT *
RES
(Internal and external)
EXTAL
STBY
VCC
2.7 V
V
IH
φ
Note: The external clock output stabilization delay time (t
DEXT ) includes a RES pulse width (t RESW ).
Figure 26.8 Timing of External Clock Output Stabilization Delay Time
t
EXCLH
t
EXCLL
t
EXCLr
t
EXCLf
V
CC
× 0.5
EXCL
Figure 26.9 Subclock Input Timing