Datasheet

Section 26 Electrical Characteristics
Rev. 2.00 Sep. 28, 2009 Page 829 of 870
REJ09B0429-0200
26.3.3 Bus Timing
Table 26.8 shows the bus timing. In subclock (φSUB = 32.768 kHz) operation, external expansion
mode operation cannot be guaranteed.
Table 26.8 Bus Timing
Condition: VCC = 3.0 V to 3.6 V, VSS = 0 V, φ = 20 MHz to 34 MHz
Item Symbol Min. Max. Unit Test Conditions
Address delay time t
AD
⎯ 14.7 ns
Address setup time t
AS
0.5 × t
cyc
–14.7 ⎯
Figures 26.12 to
26.19
Address hold time t
AH
0.5 × t
cyc
– 9.7 ⎯
CS delay time (IOS,
CS256)
t
CSD
⎯ 14.7
AS delay time t
ASD
⎯ 14.7
HBE delay time t
HBD
⎯ t
AD
+5.0
LBE delay time t
LBD
⎯ t
AD
+5.0
RD delay time 1 t
RSD1
⎯ 14.7
RD delay time 2 t
RSD2
⎯ 14.7
Read data setup time t
RDS
14.7 ⎯
Read data hold time t
RDH
0 ⎯
Read data access time 1 t
ACC1
⎯ 1.0 × t
cyc
– 29.4
Read data access time 2 t
ACC2
⎯ 1.5 × t
cyc
– 24.7
Read data access time 3 t
ACC3
⎯ 2.0 × t
cyc
– 29.4
Read data access time 4 t
ACC4
⎯ 2.5 × t
cyc
– 24.7
Read data access time 5 t
ACC5
⎯ 3.0 × t
cyc
– 29.4
WR delay time 1 t
WRD1
⎯ 14.7
WR delay time 2 t
WRD2
⎯ 14.7
WR pulse width 1 t
WSW1
1.0 × t
cyc
– 19.6 ⎯
WR pulse width 2 t
WSW2
1.5 × t
cyc
– 19.6 ⎯
Write data delay time t
WDD
⎯ 24.7
Write data setup time t
WDS
0 ⎯
Write data hold time t
WDH
0.5 × t
cyc
– 5 ⎯
WAIT setup time t
WTS
24.7 ⎯
WAIT hold time t
WTH
5 ⎯