Datasheet

Section 26 Electrical Characteristics
Rev. 2.00 Sep. 28, 2009 Page 838 of 870
REJ09B0429-0200
26.3.4 Multiplex Bus Timing
Table 26.9 shows the Multiplex bus interface timing. In subclock (φSUB = 32.768 kHz) operation,
external expansion mode operation cannot be guaranteed.
Table 26.9 Multiplex Bus Timing
Condition: VCC = 3.0 V to 3.6 V, VSS = 0 V, φ = 20 MHz to 34 MHz
Item Symbol Min.. Max. Unit Test Conditions
Address delay time t
AD
— 14.7 ns Figures 26.20,
Address setup time 2 t
AS2
0.5 × t
cyc
− 14.7 — 26.21
Address hold time 2 t
AH2
0.5 × t
cyc
− 9.7 —
CS delay time
(IOS, CS256)
t
CSD
— 14.7
AH delay time t
AHD
— 14.7
RD delay time 1 t
RSD1
— 14.7
RD delay time 2 t
RSD2
— 14.7
Read data setup time t
RDS
14.7 —
Read data hold time t
RDH
0 —
Read data access time 2 t
ACC2
— 1.5 × t
cyc
− 24.4
Read data access time 4 t
ACC4
— 2.5 × t
cyc
− 24.4
Read data access time 6 t
ACC6
— 3.5 × t
cyc
− 24.4
Read data access time 7 t
ACC7
— 4.5 × t
cyc
− 24.4
WR delay time 1 t
WRD1
— 14.7
WR delay time 2 t
WRD2
— 14.7
WR pulse width time 1 t
WSW1
1.0 × t
cyc
− 19.6 —
WR pulse width time 2 t
WSW2
1.5 × t
cyc
− 19.6 —
Write data delay time t
WDD
— 24.4
Write data setup time t
WDS
0 —
Write data hold time t
WDH
0.5 × t
cyc
− 5 —