Datasheet

Section 26 Electrical Characteristics
Rev. 2.00 Sep. 28, 2009 Page 841 of 870
REJ09B0429-0200
26.3.5 Timing of On-Chip Peripheral Modules
Tables 26.10 to 26.13 show the on-chip peripheral module timing. The on-chip peripheral modules
that can be operated by the subclock (φSUB = 32.768 kHz) are I/O ports, external interrupts (NMI,
IRQ0 to IRQ15), watchdog timer, and 8-bit timer (channels 0 and 1) only.
Table 26.10 Timing of On-Chip Peripheral Modules
Condition: VCC = 3.0 V to 3.6 V, VSS = 0 V, φ SUB = 32.768 kHz*, φ = 20 MHz to 34 MHz
Item Symbol Min. Max. Unit Test Conditions
I/O ports Output data delay time t
PWD
⎯ 29.4 ns
Input data setup time t
PRS
19.6 ⎯
Input data hold time t
PRH
19.6 ⎯
Figure 26.22
PWMX Timer output delay time t
PWOD
⎯ 29.4 ns Figure 26.23
SCI Input clock cycle Asynchronous t
Scyc
4 ⎯ t
cyc
Synchronous 6 ⎯
Input clock pulse width t
SCKW
0.4 0.6 t
Scyc
Input clock rise time t
SCKr
⎯ 1.5 t
cyc
Input clock fall time t
SCKf
⎯ 1.5
Figure 26.24
Transmit data delay time
(synchronous)
t
TXD
⎯ 29.4 ns
Receive data setup time
(synchronous)
t
RXS
19.6 ⎯
Receive data hold time
(synchronous)
t
RXH
19.6 ⎯
Figure 26.25
A/D
converter
Trigger input setup time t
TRGS
19.6 ⎯ ns Figure 26.26
WDT RESO output delay time t
RESD
⎯ 50 ns Figure 26.27
RESO output pulse width t
RESOW
132 ⎯ t
cyc
Note: * Only the peripheral modules that can be used in subclock operation.