Datasheet

Appendix
Rev. 2.00 Sep. 28, 2009 Page 853 of 870
REJ09B0429-0200
Appendix
A. I/O Port States in Each Processing State
Table A.1 I/O Port States in Each Processing State
MCU Operating
Mode
Port Name
Pin Name
EXPE Setting
Reset
Hardware
Standby Mode
Software
Standby Mode Sleep Mode
Program
Execution State
Port 1 0 / 1 (DDR=0) kept kept I/O port
A7 to A0 1 (DDR=1)
T T
kept* kept* Address output
Port 2 0 / 1 (DDR=0) kept kept I/O port
A15 to A8 1 (DDR=1)
T T
kept* kept* Address output
Port 3 0 kept kept I/O port
D15 to D8 1
T T
T T D15 to D8
Port 4 0 T T kept kept I/O port
Port 5 X T T kept kept I/O port
Port 6 0 / 1 (8 bits) kept kept I/O port
D7 to D0 1 (16 bits)
T T
T T D7 to D0
Port 7 X T T T T Input port
Port 8 X T T kept kept I/O port
Port 97 0 kept kept I/O port
WAIT 1 (CS256E=0)
T T
T T WAIT
CS256 1 (CS256E=1) H H CS256
Port 96 0 Input port
EXCL 1 (DDR=0)
T T
EXCL
φ 1 (DDR=1)
T T
H φ output φ
Port 95 0 kept kept I/O port
AS, IOS
1
T T
H H AS/IOS
Port 94 0 kept kept I/O port
WR, HWR 1
T T
H H WR, HWR
Port 93 0 kept kept I/O port
RD 1
T T
H H RD