Datasheet

Rev. 2.00 Sep. 28, 2009 Page 857 of 870
REJ09B0429-0200
Main Revisions for This Edition
Item Page Revision (See Manual for Details)
3.1 Operating Mode
Selection
55 Description amended
This MCU supports three operating modes (modes 2, 4, and
6). …
Table 3.1 MCU
Operating Mode
Selection
Table amended
MCU
Operating
Mode
CPU
Operating
Mode Description
2 1 1 0 Advanced Extended mode with on-chip ROM
Single-chip mode
4 0 0 0 — Flash programming/erasing
6 0 1 0 Emulation On-chip emulation mode
MD1 MD0
MD2
3.3.1 Mode 2 60 Description amended
• Multiplex extended mode
When 8-bit bus is specified, port 2 functions as the port for
address output and data input/output regardless of the
setting of the data direction register (DDR). Port 1 can be
used as a general port.
5.5 Interrupt Exception
Handling Vector Table
Table 5.3 Interrupt
Sources, Vector
Addresses, and Interrupt
Priorities
83 Note added
Note: Vector numbers not listed above are reserved by the
system.
6.5.1 Data Size and
Data Alignment
(1) 8-Bit Access Space
119 Description amended
The upper data bus (AD15 to AD8) is used in address-data
multiplex extended mode.
6.5.2 Valid Strobes
Table 6.13 Data Buses
Used and Valid Strobes
121 Table amended
Area
Valid
Strobe
Upper Data Bus
(D15 to D8/
AD15 to AD8)
Lower Data
Bus (D7 to
D0/AD7 to
AD0)
8-bit access
space
Byte Read
Write
—
—
RD
HWR
Valid Ports or others
Ports or others
8-bit access
space
(in address-
data multiplex
extended
mode)
Byte Read
Write
—
—
RD
HWR
Valid Ports or others
Read/
Write Address
Access
Size