Datasheet

Rev. 2.00 Sep. 28, 2009 Page 860 of 870
REJ09B0429-0200
Item Page Revision (See Manual for Details)
15.4.3 Initialization of
the SCIF
Figure 15.4 Example of
Data Transmission
Flowchart
428 Figure amended
[1] Confirm that the THRE flag in FLSR is 1, and write transmit
data to FTHR. When FIFOs are used, write 1-byte to 16-byte
transmit data. When the OUT2 bit in FMCR and the ETBEI bit
in FIER are set to 1, an FTHR empty interrupt occurs. When
data is written to FTHR, it is transferred automatically to FTSR.
The data is then transmitted from the TxDF pin in the order of
the start bit, transmit data, parity bit, and stop bit.
Figure 15.5 Example of
Data Reception
Flowchart
429 Figure amended
Start reception
Read DR flag in FLSR
Read FRBR
Error processing
DR = 1
RXFIFOERR = 1,
BI = 1, FE = 1,
PE = 1, or OE = 1
Yes
No
No
No
No
Yes
Yes
All data read
(End of reception or reception standby)
Yes
Initialization
[1]
[2]
[3]
[4]
DR = 0
[1] Confirm that the DR flag in FLSR is 1 to ensure that
receive data is in the buffer. When the OUT2 bit in
FMCR and the ERBFI bit in FIER are set to 1, a
receive data ready interrupt occurs.
[2] Read the RXFIFOERR, BI, FE, PE, and OE flags in
FLSR to ensure that no error has occurred. If an
error has occurred, perform error processing. When
the OUT2 bit in FMCR and the ELSI bit in FIER are
set to 1, a receive line status interrupt occurs.
[3] Read the receive data in FRBR.
[4] Check the DR flag in FLSR. When the DR flag is
cleared to 0 and all data has been read, data reception
is complete.
Read RXFIFOERR, BI, FE, and
OE flags in FLSR
Read DR flag in FLSR