Datasheet

Rev. 2.00 Sep. 28, 2009 Page 861 of 870
REJ09B0429-0200
Item Page Revision (See Manual for Details)
15.4.4 Data
Transmission/Reception
with Flow Control
Figure 15.10 Example
of Data Reception
Flowchart
434 Figure amended
Read FLSR
Receive data ready interrupt
Read receive FIFO
Read FLSR
Error processing
(Transmission/reception standby flow)
BI = 1, FE = 1,
PE = 1, or OE = 1
DR = 0
No
Yes
[2]
[1]
[3]
[4]
[1] When data is received, a receive data ready
interrupt occurs. Go to the data reception flow
by using this interrupt trigger.
[2] Confirm that the BI, FE, PE, and OE flags in
FLSR are all cleared. If any one of these flags
is set to 1, perform error processing.
[3] Read the receive FIFO.
[4] Check the DR flag in FLSR. When the DR flag
is cleared and all of the data has been read, data
reception is complete.
17.4.4 Master Receive
Operation
Figure 17.12 Stop
Condition Issuance
Timing Example in
Master Receive Mode
(MLS = WAIT = 0, HNDS
= 1)
490 Figure amended
SDA
(master output)
SDA
(slave output)
21
4
3
65
8
7
9978
A
A
Bit 7Bit 1
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
IRIC
ICDRF
ICDRR
SCL
(master output)
Data 3
Data 2
Data 1 Data 2
Data 3
[9] IRIC clear
User processing
IRTR
[8] [3]
Bit 0
[11] BBSY cleared to 0 and
SCP cleared to 0
(Stop condition instruction issuance)
[4] IRIC clear [7] ICDR read
(Data 2)
[10] ICDR read
(Data 3)
[6] ACKB set to 1
Bit 0
Stop condition generation
SCL is fixed low until ICDR is read SCL is fixed low until ICDR is read
17.6 Usage Notes
Table 17.13 I
2
C Bus
Timing (with Maximum
Influence of t
Sr
/t
Sf
)
518 Table amended
Item
Time Indication (at Maximum Transfer Rate) [ns]
t
SCLLO
0.5 t
SCLO
(-t
Sf
) Standard mode
High-speed mode
-250
-250
4700
1300
4750
950*
1
4230
870*
1
4456
926*
1
t
BUFO
0.5 t
SCLO
-1 t
cyc
( -t
Sr
)
Standard mode
High-speed mode
-1000
-300
4700
1300
3950*
1
850*
1
3440*
1
780*
1
3676*
1
847*
1
t
cyc
Indication
φ = 20 MHz φ = 25 MHz φ = 34 MHz
I
2
C Bus
Specifi-
cation (Min.)
t
Sr
/t
Sf
Influence
(Max.)