Datasheet

Rev. 2.00 Sep. 28, 2009 Page 862 of 870
REJ09B0429-0200
Item Page Revision (See Manual for Details)
18.3.2 Host Interface
Control Registers 2 and
3 (HICR2 and HICR3)
• HICR3
546 Table amended
Bit
7
6
5
4
3
2
1
0
R
R
R
R
R
R
R
R
—
—
—
—
—
—
—
—
LFRAME
CLKRUN
SERIRQ
LRESET
LPCPD
PME
LSMI
LSCI
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Bit Name Initial Value Slave DescriptionHost
R/W
0: LFRAME Pin state is low level
1: LFRAME Pin state is high level
0: CLKRUN Pin state is low level
1: CLKRUN Pin state is high level
0: SERIRQ Pin state is low level
1: SERIRQ Pin state is high level
0: LRESET Pin state is low level
1: LRESET Pin state is high level
0: LPCPD Pin state is low level
1: LPCPD Pin state is high level
0: PME Pin state is low level
1: PME Pin state is high level
0: LSMI Pin state is low level
1: LSMI Pin state is high level
0: LSCI Pin state is low level
1: LSCI Pin state is high level
24.2 Mode Transitions
and LSI States
Figure 24.1 Mode
Transition Diagram
777 Note amended
* NMI, IRQ0 to IRQ15
25.2 Register Bits 798 Table amended
Register
Abbreviation Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module
SMSTPB15
SMSTPB7
SUBMSTPBH
SUBMSTPBL
SMSTPB14
SMSTPB6
SMSTPB13
SMSTPB5
SMSTPB12
SMSTPB4
SMSTPB11
SMSTPB3
SMSTPB10
SMSTPB2
SMSTPB9
SMSTPB1
SMSTPB8
SMSTPB0
SYSTEM
26.2 DC Characteristics
Table 26.2 DC
Characteristics (1)
818 Table amended
Item
Input
high
voltage
RES, STBY, NMI, FWE, MD2,
MD1, MD0
EXTAL
Port 7
SCL5 to SCL0, SDA5 to SDA0,
Ports 80 to 83, C0 to C5, D6,
D7