Datasheet

Rev. 2.00 Sep. 28, 2009 Page 866 of 870
REJ09B0429-0200
Data transfer instructions.......................... 35
Download pass/fail result parameter....... 664
DTC vector table .................................... 165
E
Effective address................................. 45, 49
Effective address extension ...................... 44
ERI1........................................................ 386
ERI2........................................................ 386
Error protection ...................................... 706
Exception handling................................... 63
Exception handling vector table ............... 64
Extended control register (EXR) .............. 27
External clock......................................... 765
F
Flash erase block select parameter.......... 671
Flash MAT configuration ....................... 647
Flash multipurpose address area
parameter ................................................ 668
Flash multipurpose data destination
parameter ................................................ 668
Flash pass/fail parameter ........................ 672
Flash programming/erasing frequency
parameter ................................................ 666
FOVI....................................................... 282
Framing error.......................................... 354
G
General registers....................................... 26
H
Hardware protection ............................... 704
Hardware standby mode ......................... 783
I
I/O ports.................................................. 179
I/O select signals.....................................118
I
2
C bus formats .......................................481
I
2
C bus interface (IIC).............................449
Immediate .................................................47
Input pull-up MOS control register.........179
Input pull-up MOSs ................................179
Instruction set............................................33
Interface ..................................................327
Internal block diagram................................2
Interrupt control modes............................. 84
Interrupt controller.................................... 71
Interrupt exception handling.....................68
Interrupt exception handling sequence......91
Interrupt exception handling
vector table................................................82
Interrupt mask bit...................................... 28
interrupt mask level ..................................27
Interval timer mode.................................320
IRQ15 to IRQ0 interrupts .........................80
L
Logic operations instructions.................... 38
LPC interface (LPC)...............................529
LPC interface clock start request ............614
LSI internal states in each mode .............778
M
Master receive operation.........................487
Master transmit operation ....................... 483
Medium-speed mode...............................779
Memory indirect .......................................48
Mode comparison ...................................646
Mode transition diagram.........................777
Module stop mode ..................................784
Multiply-accumulate register (MAC) .......29