Datasheet

Section 3 MCU Operating Modes
Rev. 2.00 Sep. 28, 2009 Page 57 of 870
REJ09B0429-0200
3.2.2 System Control Register (SYSCR)
SYSCR selects a system pin function, monitors a reset source, selects the interrupt control mode
and the detection edge for NMI, enables or disables register access to the on-chip peripheral
modules, and enables or disables on-chip RAM address space.
Bit Bit Name
Initial
Value
R/W Description
7 CS256E 0 R/W Chip Select 256 Enable
Enables or disables P97/WAIT/CS256 pin function in
extended mode.
0: P97/WAIT pin
WAIT pin function is selected by the settings of
WSCR and WSCR2.
1: CS256 pin
Outputs low when a 256-kbyte expansion area of
addresses H'F80000 to H'FBFFFF is accessed.
6 IOSE 0 R/W IOS Enable
Enables or disables AS/IOS pin function in extended
mode.
0: AS pin
Outputs low when an external area is accessed.
1: IOS pin
Outputs low when an IOS expansion area of
addresses H'FFF000 to H'FFF7FF is accessed.
5
4
INTM1
INTM0
0
0
R
R/W
These bits select the control mode of the interrupt
controller. For details on the interrupt control modes, see
section 5.6, Interrupt Control Modes and Interrupt
Operation.
00: Interrupt control mode 0
01: Interrupt control mode 1
10: Setting prohibited
11: Setting prohibited