Datasheet

Section 19 Synchronous Serial Communication Unit (SSU)
R01UH0310EJ0500 Rev. 5.00 Page 1045 of 1384
Sep 25, 2012
H8S/2426, H8S/2426R, H8S/2424 Group
19.3.5 SS Status Register (SSSR)
SSSR is a status flag register for interrupts.
Bit Bit Name
Initial
Value R/W Description
7 ⎯ 0 ⎯ Reserved
This bit is always read as 0. The write value should
always be 0.
6 ORER 0 R/W Overrun Error
If the next data is received while RDRF = 1, an overrun
error occurs, indicating abnormal termination. SSRDR
stores 1-frame receive data before an overrun error
occurs and loses data to be received later. While
ORER = 1, consecutive serial reception cannot be
continued. Serial transmission cannot be continued,
either.
[Setting condition]
When one byte of the next reception is completed with
RDRF = 1
[Clearing condition]
When writing 0 after reading ORER = 1
5, 4 ⎯ All 0 R/W Reserved
These bits are always read as 0. The write value should
always be 0.
3 TEND 1 R Transmit End
[Setting condition]
• When the last bit of transmit data is transmitted
while the TENDSTS bit in SSCR2 is cleared to 0
and the TDRE bit is set to 1
• After the last bit of transmit data is transmitted while
the TENDSTS bit in SSCR2 is set to 1 and the
TDRE bit is set to 1
[Clearing conditions]
• When writing 0 after reading TEND = 1
• When writing data to SSTDR