Datasheet

Section 26 Boundary Scan (JTAG)
Rev. 2.00 Aug. 20, 2008 Page 1019 of 1198
REJ09B0403-0200
26.2 Input/Output Pins
Table 26.1 shows the JTAG pin configuration.
Table 26.1 Pin Configuration
Pin Name Abbreviation I/O Function
Test clock ETCK Input Test clock input
Provides an independent clock supply to the
JTAG. As the clock input to the ETCK pin is
supplied directly to the JTAG, a clock waveform
with a duty cycle close to 50% should be input.
For details, see section 31, Electrical
Characteristics.
Test mode select ETMS Input Test mode select input
Sampled on the rise of the ETCK pin. The ETMS
pin controls the internal state of the TAP
controller.
Test data input ETDI Input Serial data input
Performs serial input of instructions and data for
JTAG registers. ETDI is sampled on the rise of
the ETCK pin.
Test data output ETDO Output Serial data output
Performs serial output of instructions and data
from JTAG registers. Transfer is performed in
synchronization with the ETCK pin. If there is no
output, the ETDO pin goes to the high-
impedance state.
Test reset ETRST Input Test reset input signal
Initializes the JTAG asynchronously.