Datasheet

Section 26 Boundary Scan (JTAG)
Rev. 2.00 Aug. 20, 2008 Page 1045 of 1198
REJ09B0403-0200
26.6 Usage Notes
1. A reset must always be executed by driving the ETRST pin to 0, regardless of whether or not
the JTAG is to be activated. The ETRST pin must be held low for 20 ETCK clock cycles. For
details, see section 31, Electrical Characteristics. To activate the JTAG after a reset, drive the
ETRST pin to 1 and specify the ETCK, ETMS, and ETDI pins to any value. If the JTAG is not
to be activated, drive the ETRST, ETCK, ETMS, and ETDI pins to 1 or the high-impedance
state.
2. The following must be considered when the power-on reset signal is applied to the ETRST pin.
 The reset signal must be applied at power-on.
 To prevent the LSI system operation from being affected by the ETRST pin of the board
tester, circuits must be separated.
 Alternatively, to prevent the ETRST pin of the board tester from being affected by the LSI
system reset, circuits must be separated.
Figure 26.3 shows a design example of the reset signal circuit wherein no reset signal
interference occurs.
Power-on
reset circuit
Board edge pin
System reset
ETRST
RES
ETRST
This LSI
Figure 26.3 Reset Signal Circuit Without Reset Signal Interference