Datasheet

Section 27 Clock Pulse Generator
Rev. 2.00 Aug. 20, 2008 Page 1053 of 1198
REJ09B0403-0200
27.7 Clock Select Circuit
The clock select circuit selects the system clock that is used in this LSI.
A clock generated by the oscillator, to which the EXTAL and XTAL pins are input, and multiplied
by the PLL circuit is selected as a system clock when returning from high-speed mode, medium-
speed mode, sleep mode, the reset state, or standby mode.