Datasheet

Section 28 Power-Down Modes
Rev. 2.00 Aug. 20, 2008 Page 1056 of 1198
REJ09B0403-0200
28.1 Register Descriptions
Power-down modes are controlled by the following registers. To access SBYCR, LPWRCR,
MSTPCRH, and MSTPCRL, the FLSHE bit in the serial timer control register (STCR) must be
cleared to 0. For details on STCR, see section 3.2.3, Serial Timer Control Register (STCR).
• Standby control register (SBYCR)
• Low power control register (LPWRCR)
• Module stop control register H (MSTPCRH)
• Module stop control register L (MSTPCRL)
• Module stop control register A (MSTPCRA)
• Sub-chip module stop control register BH, BL (SUBMSTPBH, SUBMSTPBL)
28.1.1 Standby Control Register (SBYCR)
SBYCR controls power-down modes.
Bit Bit Name
Initial
Value
R/W Description
7 SSBY 0 R/W Software Standby
Specifies the operating mode to be entered after
executing the SLEEP instruction.
When the SLEEP instruction is executed in high-speed
mode or medium-speed mode:
0: Shifts to sleep mode
1: Shifts to software standby mode
Note that the SSBY bit is not changed even if a mode
transition occurs by an interrupt.