Datasheet

Section 29 List of Registers
Rev. 2.00 Aug. 20, 2008 Page 1072 of 1198
REJ09B0403-0200
29.1 Register Addresses (Address Order)
The data bus width indicates the numbers of bits by which the register is accessed. The number of
access states indicates the number of states based on the specified reference clock.
Note: Access to undefined or reserved addresses is prohibited. Since operation or continued
operation is not guaranteed when these registers are accessed, do not attempt such access.
Register Name Abbreviation
Number
of Bits Address Module
Data
Bus
Width
Number
of Access
States
EtherC mode register ECMR 32 H'F900 EtherC 16 8
EtherC status register ECSR 32 H'F904 EtherC 16 8
EtherC interrupt permission register ECSIPR 32 H'F908 EtherC 16 8
PHY interface register PIR 32 H'F90C EtherC 16 8
MAC address high register MAHR 32 H'F910 EtherC 16 8
MAC address low register MALR 32 H'F914 EtherC 16 8
Receive frame length register RFLR 32 H'F918 EtherC 16 8
PHY status register PSR 32 H'F91C EtherC 16 8
Transmit retry over counter register TROCR 32 H'F920 EtherC 16 8
Delayed collision detect counter
register
CDCR 32 H'F924 EtherC 16 8
Lost carrier counter register LCCR 32 H'F928 EtherC 16 8
Carrier not detect counter register CNDCR 32 H'F92C EtherC 16 8
CRC error frame counter register CEFCR 32 H'F934 EtherC 16 8
Frame receive error counter register FRECR 32 H'F938 EtherC 16 8
Too-short frame receive counter
register
TSFRCR 32 H'F93C EtherC 16 8
Too-long frame receive counter
register
TLFRCR 32 H'F940 EtherC 16 8
Residual-bit frame counter register RFCR 32 H'F944 EtherC 16 8
Multicast address frame counter
register
MAFCR 32 H'F948 EtherC 16 8
IPG register IPGR 32 H'F954 EtherC 16 8
Automatic PAUSE frame set register APR 32 H'F958 EtherC 16 8
Manual PAUSE frame set register MPR 32 H'F95C EtherC 16 8