Datasheet

Section 31 Electrical Characteristics
Rev. 2.00 Aug. 20, 2008 Page 1126 of 1198
REJ09B0403-0200
Table 31.5 External Clock Input Conditions
Conditions: VCC = 3.0 V to 3.6 V, VSS = 0 V, φ = 20 MHz to 34 MHz
Item Symbol Min. Max. Unit
Test
Conditions
External clock input low level
pulse width
t
EXL
58.8

ns
External clock input high level
pulse width
t
EXH
58.8

ns
External clock input rising time t
EXr

5 ns
External clock input falling time t
EXf

5 ns
Figure 31.7
Clock low level pulse width t
CL
0.4 0.6 t
cyc
Clock high level pulse width t
CH
0.4 0.6 t
cyc
Figure 31.4
External clock output
stabilization delay time
t
DEXT
* 500

µs Figure 31.8
Note: * t
DEXT
includes a RES pulse width (t
RESW
).
Table 31.6 Subclock Input Conditions
Conditions: VCC = 3.0 V to 3.6 V, VSS = 0 V, φ = 20 MHz to 34 MHz
Item Symbol Min. Typ. Max. Unit
Test
Conditions
Subclock input low level pulse
width
t
EXCLL

15.26

µs
Subclock input high level pulse
width
t
EXCLH

15.26

µs
Subclock input rising time t
EXCLr
 
10 ns
Subclock input falling time t
EXCLf
 
10 ns
Figure 31.9
Clock low level pulse width t
CL
0.4

0.6 t
cyc
Clock high level pulse width t
CH
0.4

0.6 t
cyc
Figure 31.4