Datasheet

Section 31 Electrical Characteristics
Rev. 2.00 Aug. 20, 2008 Page 1128 of 1198
REJ09B0403-0200
t
EXH
t
EXL
t
EXr
t
EXf
V
CC
× 0.5
EXTAL
Figure 31.7 External Clock Input Timing
t DEXT *
RES
(Internal and external)
EXTAL
STBY
VCC
2.7 V
V
IH
φ
Note: The external clock output stabilization delay time (t
DEXT ) includes a RES pulse width (t RESW ).
Figure 31.8 Timing of External Clock Output Stabilization Delay Time