Datasheet

Section 31 Electrical Characteristics
Rev. 2.00 Aug. 20, 2008 Page 1142 of 1198
REJ09B0403-0200
φ
AH
RD
(Read)
T
1
T
2
AD15 to AD0
(Read)
D15 to D0
D15 to D0
A15 to A0
A15 to A0
HWR, LWR
(Write)
AD15 to AD0
(Write)
T
3
T
4
t
CSD
t
AHD
t
RSD1
t
ACC2
t
ACC6
t
AS2
t
AD
t
AD
t
AH2
t
WRD2
t
WDD
t
WDH
t
RSD2
t
WRD2
t
WSW1
t
RDS
t
RDH
IOS, CS256
Figure 31.20 Multiplex Bus Timing/Data 2-State Access