Datasheet

Section 31 Electrical Characteristics
Rev. 2.00 Aug. 20, 2008 Page 1145 of 1198
REJ09B0403-0200
Table 31.10 Timing of On-Chip Peripheral Modules
Conditions: VCC = 3.0 V to 3.6 V, VSS = 0 V, φ SUB = 32.768 kHz*, φ = 20 MHz to 34 MHz
Item Symbol Min. Max. Unit Test Conditions
I/O ports Output data delay time t
PWD

29.4 ns
Input data setup time t
PRS
19.6

Input data hold time t
PRH
19.6

Figure 31.22
PWMX Timer output delay time t
PWOD

29.4 ns Figure 31.23
SCI Asynchronous t
Scyc
4

t
cyc
Input clock
cycle
Synchronous 6

Input clock pulse width t
SCKW
0.4 0.6 t
Scyc
Input clock rise time t
SCKr

1.5 t
cyc
Input clock fall time t
SCKf

1.5
Figure 31.24
Transmit data delay time
(synchronous)
t
TXD

29.4 ns
Receive data setup time
(synchronous)
t
RXS
19.6

Receive data hold time
(synchronous)
t
RXH
19.6

Figure 31.25
Receive data setup time
(synchronous)
t
RXS
30.0

Figure 31.25 SCI
(multiplexed
with P51)
Receive data hold time
(synchronous)
t
RXH
30.0

A/D
converter
Trigger input setup time t
TRGS
19.6

Figure 31.26
WDT RESO output delay time t
RESD

50
ns
RESO output pulse width t
RESOW
132

t
cyc
Figure 31.27
Note: * Only the peripheral modules that can be used in subclock operation.