Datasheet

Section 31 Electrical Characteristics
Rev. 2.00 Aug. 20, 2008 Page 1146 of 1198
REJ09B0403-0200
Table 31.11 Timing of On-Chip Peripheral Modules (2)
Conditions: VCC = 3.0 V to 3.6 V, VSS = 0 V, φ = 20 MHz to 34 MHz
Item Symbol Min. Max. Unit Test Conditions
SSU Clock cycle time Master t
SUcyc
4 256 t
cyc
Figure 31.28
Slave 4 256 Figure 31.29
Clock high pulse width Master t
HI
80

ns Figure 31.30
Slave 80

Figure 31.31
Clock low pulse width Master t
LO
80

ns
Slave 80

Clock rising time t
RISE

20 ns
Clock falling time t
FALL

20 ns
Data input setup time Master t
SU
25

ns
Slave 30

Data input hold time Master t
H
10

ns
Slave 10

SCS setup time Master t
LEAD
2.5

t
cyc
Slave 2.5

SCS hold time Master t
LAG
2.5

t
cyc
Slave 2.5

Data output delay time Master t
OD

40 ns
Slave

40
Data output hold time Master t
OH
30

ns
Slave 30

Master t
TD
2.5

t
cyc
Consecutive transmit
delay time
Slave
2.5

Slave access time t
SA

1 t
cyc
Figure 31.30
Slave out release time t
REL

1 t
cyc
Figure 31.31