Datasheet

Section 31 Electrical Characteristics
Rev. 2.00 Aug. 20, 2008 Page 1154 of 1198
REJ09B0403-0200
Table 31.14 Ethernet Controller Signal Timing
Conditions: VCC = 3.0 V to 3.6V, VSS = 0 V, φ = 20 MHz to 34 MHz
Item Symbol Min. Typ. Max. Unit Test Conditions
RM_REF-CLK cycle time T
ck
20
 
ns Figure 31.34
RM_REF-CLK frequency
 
50 50 +
100 ppm
MHz
RM_REF-CLK duty cycle

35

65 %
RM_REF-CLK rise/fall time T
ckr
/T
ckf
0.5

3.5 ns
RM_xxxx*
1
output delay time T
co
2.5

12.5
RM_xxxx*
1
setup time T
su
3
 
RM_xxxx*
1
hold time T
hd
1
 
RM_xxxx*
1
rise/fall time T
r
/T
f
0.5

6
MDIO setup time t
MDIOS
10
 
Figure 31.38
MDIO hold time t
MDIOH
10
 
MDIO output data hold time*
2
t
MDIODH
5

18 Figure 31.39
WOL output delay time t
WOLD
1

20 Figure 31.40
Notes: 1. RM_TXD-EN, RM_TXD1, RM_TXD0, RM_CRS-DV, RM_RXD1, RM_RXD0, and
RM_RX-ER
2. This specification must be satisfied by the user by software.
Tck
Tco
Tf
Tsu Thd
Tckr
Tr
90 %
50 %
10 %
90 %
50 %
10 %
Tckf
RM_REF-CLK
Signal
Signal
transition
Signal
transition
Signal
transition
Signal
RM_xxxx
Figure 31.34 Timing of RM_REF-CLK and RMII Signals