Datasheet

Section 31 Electrical Characteristics
Rev. 2.00 Aug. 20, 2008 Page 1159 of 1198
REJ09B0403-0200
Table 31.16 JTAG Timing
Conditions: VCC = 3.0 V to 3.6 V, VSS = 0 V, φ = 20 MHz to 34 MHz
Item Symbol Min. Max. Unit Test Conditions
ETCK clock cycle time t
TCKcyc
29.4* 50* ns Figure 31.42
ETCK clock high pulse width t
TCKH
15

ETCK clock low pulse width t
TCKL
15

ETCK clock rise time t
TCKr

5
ETCK clock fall time t
TCKf

5
ETRST pulse width t
TRSTW
20

t
cyc
Figure 31.43
Reset hold transition pulse width t
RSTHW
3

ETMS setup time t
TMSS
20

ns Figure 31.44
ETMS hold time t
TMSH
20

ETDI setup time t
TDIS
20

ETDI hold time t
TDIH
20

ETDO data delay time t
TDOD

20
Note: * When t
cyc
≤ t
TCKcyc
ETCK
t
TCKcyc
t
TCKH
t
TCKf
t
TCKL
t
TCKr
Figure 31.43 JTAG ETCK Timing