Datasheet

Appendix
Rev. 2.00 Aug. 20, 2008 Page 1165 of 1198
REJ09B0403-0200
Appendix
A. I/O Port States in Each Processing State
Table A.1 I/O Port States in Each Processing State
MCU Operating
Mode
Port Name
Pin Name
EXPE Setting
Reset
Hardware
Standby Mode
Software
Standby Mode Sleep Mode
Program
Execution State
Port 1 0 / 1 (DDR=0) kept kept I/O port
A7 to A0 1 (DDR=1)
T T
kept* kept* Address output
Port 27 to 24 X T T kept kept I/O port
Port 23 to 20 0 / 1 (DDR=0) kept kept I/O port
A11 to A8 1 (DDR=1)
T T
kept* kept* Address output
Port 3 0 kept kept I/O port
D15 to D8 1
T T
T T D15 to D8
Port 47 to 44 0 kept kept I/O port
A15 to A12 1
T T
kept* kept* A15 to A12
Port 43 to 40 0 / 1 (8 bits) kept kept I/O port
D7 to D4 1 (16 bits)
T T
T T D7 to D4
Port 57 0 kept kept I/O port
WR, HWR 1
T T
H H WR, HWR
Port 56 0 Input port
EXCL 1 (DDR=0)
T T
EXCL
φ 1 (DDR=1)
T T
H φ output φ
Port 55 to 50 X T T kept kept I/O port
Port 67 to 64 X T T kept kept I/O port
Port 63 to 60 0 / 1 (8 bits) kept kept I/O port
D3 to D0 1 (16 bits)
T T
T T D3 to D0
Port 7 X T T T T Input port
Port 8 X T T kept kept I/O port