Datasheet

Rev. 2.00 Aug. 20, 2008 Page 1176 of 1198
REJ09B0403-0200
Item Page Revision (See Manual for Details)
Section 3 MCU
Operating Modes
3.2.3 Serial Timer
Control Register (STCR)
67 Added
Bit Bit Name
Initial
Value
R/W Description
3 FLSHE 0 R/W Flash Memory Control Register Enable
Enables or disables CPU access for flash
memory registers (FCCS, FPCS, FECS,
FKEY, FMATS, FTDAR), control registers of
power-down states (SBYCR, LPWRCR,
MSTPCRH, MSTPCRL), and control
registers of on-chip peripheral modules
(BCR2, WSCR2, PCSR, SYSCR2).
0: Area from H'FFFE88 to H'FFFE8F is
reserved.
Area from H'FFFEA0 to H'FFFEBF is
allocated to registers of AD, serial
multiplexed functions, and I/O ports.
Area from H'FFFF80 to H'FFFF87 is
allocated to control registers of power-
down states and on-chip peripheral
modules.
1: Area from H'FFFE88 to H'FFFE8F is
allocated to control registers of flash
memory.
Area from H'FFFEA0 to H'FFFEBF is
reserved.
Area from H'FFFF80 to H'FFFF87 is
reserved.
Section 4 Exception
Handling
4.3.3 On-Chip
Peripheral Modules after
Reset is Cancelled
75 After a reset is cancelled, the module stop control registers
(MSTPCR, MSTPCRA, and SUBMSTPB, and SUBMSTPA) are
initialized, …