Datasheet

Rev. 2.00 Aug. 20, 2008 Page 1177 of 1198
REJ09B0403-0200
Item Page Revision (See Manual for Details)
Section 5 Interrupt
Controller
Table 5.2
Correspondence
between Interrupt
Source and ICR
82 Amended
Register
Bit ICRC ICRD
7 SCI_3 IRQ8 to IRQ11
2 IIC_2, IIC_3 PECI*
2
1 LPC SCIF
0 USB*
1
—
[Legend]
n: A to D
: Reserved. The write value should always be 0.
Notes: 1. Supported only by the H8S/2472 Group.
2. Supported only by the H8S/2472 Group and the
H8S/2462 Group.
Table 5.3 Interrupt
Sources, Vector
Addresses, and
Interrupt Priorities
92 Amended
Origin of Interrupt Source
PECI*
2
USB*
1
Notes: 1. Supported only by the H8S/2472 Group.
2. Supported only by the H8S/2472 Group and the
H8S/2462 Group.
Section 8 I/O Ports
8.1 I/O Ports for the
H8S/2472 Group
189 Description amended
Table 8.1 is a summary of the port functions. … For port A pins
and D0 to D5 pins, the on/off status of the input pull-up MOS is
controlled by their respective DDR and the output data register
(ODR). Ports 1 to 4, and 6 have an input pull-up MOS control
register (PCR), …
8.1.9 Port 9
(3) Pin Functions
237 Deleted
• P97/WAIT/CS256
The pin function is switched as shown below according to
the operating mode and the combination of the CS256E bit
in SYSCR, the WMS1 bit in WSCR, the WMS21 bit in
WSCR2, and the P97DDR bit.
Operating
Mode
Extended mode
WMS1,
WMS21
All
0 Either bit is 1