Datasheet

Rev. 2.00 Aug. 20, 2008 Page 1178 of 1198
REJ09B0403-0200
Item Page Revision (See Manual for Details)
8.1.10 Port A 243 Amended
• PA5/ExIRQ5/EVENT5/A21/WOL
The pin function is switched as shown below according to the
setting of the address 18, and the PA5DDR bit.
Setting the ISS5 bit in ISSR to 1 makes the pin function as the
ExIRQ5 input pin.
When using the pin as the ExIRQ5 input, or an EVENT input
pin, clear the PA5DDR bit to 0. Though the settings for the
EVENT input pin have been made, set the PA5DDR bit to 1
when using the pin as the A21 or PA5 output pin.
When the module stop mode is cleared in both the EtherC, and
E-DMAC, this pin functions as the WOL output pin.
8.1.15 Port F 271 Amended
• PF1/RS9/MDC, PF0/RS8/MDIO
EtherC,
E-DMAC
Ether of them is stopped Both of them are stopped
PFnDDR 0 1 X
Pin function PFn input
pin
PFn output
pin
MDC output pin/
MDIO input/output pin
8.2 I/O Ports for the
H8S/2463 Group and
the H8S/2462 Group
272 Title and description amended
Table 8.9 is a summary of the port functions. … For port A pins
and D0 to D5 pins, the on/off status of the input pull-up MOS is
controlled by their respective DDR and the output data register
(ODR). Ports 1 to 4, and 6 have an input pull-up MOS control
register (PCR), …
8.2.9 Port 9
(3) Pin Functions
321 Deleted
• P97/WAIT/CS256
The pin function is switched as shown below according to
the operating mode and the combination of the CS256E bit
in SYSCR, the WMS1 bit in WSCR, the WMS21 bit in
WSCR2, and the P97DDR bit.
Operating
Mode
Extended mode
WMS1,
WMS21
All
0 Either bit is 1