Datasheet

Rev. 2.00 Aug. 20, 2008 Page 1179 of 1198
REJ09B0403-0200
Item Page Revision (See Manual for Details)
8.2.10 Port A 327 Amended
• PA5/ExIRQ5/EVENT5/A21/WOL
The pin function is switched as shown below according to the
setting of the MPDE bit in ECMR in EtherC, the address 18, and
the PA5DDR bit.
Setting the ISS5 bit in ISSR to 1 makes the pin function as the
ExIRQ5 input pin.
When using the pin as the ExIRQ5 input, or an EVENT input
pin, clear the PA5DDR bit to 0. Though the settings for the
EVENT input pin have been made, set the PA5DDR bit to 1
when using the pin as the A21 or PA5 output pin.
When the module stop mode is cleared in both the EtherC and
E-DMAC, this pin functions as the WOL output pin.
8.2.15 Port F 355 Amended
• PF1/RS9/MDC
EtherC,
E-DMAC
Either of them is stopped Both of them are
stopped
PF1DDR 0 1 X
Pin function PF1 input pin PF1 output pin MDC output pin
Section 10 16-Bit Free-
Running Timer (FRT)
Figure 10.3 Timing of
Output Compare A
Output
383 Replaced
Section 12 Watchdog
Timer (WDT)
12.3.2 Timer Control/
Status Register (TCSR)
• TCSR_0
418 Amended
Bit Bit Name Initial Value R/W
4  0 R/W