Datasheet

Rev. 2.00 Aug. 20, 2008 Page 1180 of 1198
REJ09B0403-0200
Item Page Revision (See Manual for Details)
• TCSR_1
420 Amended
Bit Bit Name Description
5 TME Timer Enable
When this bit is set to 1, TCNT starts counting.
When this bit is cleared, TCNT stops counting
and is initialized to H'00. When PSS = 1, TCNT
is not initialized. Write H'00 to TCNT to initialize
TCNT.
Section 15 Serial
Communication
Interface with FIFO
(SCIF)
15.3 Register
Descriptions
510 Register name amended
• Sub-chip module stop control register BL (SUBMSTPBL)
Table 15.2 Register
Access
510 Description in this table amended
SCIFE Bit in HICR5 0
Bit 3 in SUBMSTPBL 0 1
Figure 15.4 Example of
Data Transmission
Flowchart
531 Modified
[1] Confirm that the THRE flag in FLSR is 1, and write transmit data to
FTHR. When FIFOs are used, write 1-byte to 16-byte transmit data.
When the OUT2 bit in FMCR and the ETBEI bit in FIER are set to 1,
an FTHR empty interrupt occurs. When data is written to FTHR, it is
transferred automatically to FTSR.
The data is then transmitted from the TxDF pin in the order of the
start bit, transmit data, parity bit, and stop bit
.
Figure 15.5 Example of
DATA Reception
Flowchart
532 Modified
Read FRBR
Error processing
RXFIFOERR = 1,
BI = 1, FE = 1,
PE = 1, or OE = 1
Yes
No
Yes
[2]
[3]
[4]
Read RXFIFOERR, BI, PE and OE
flag in FLSR
Read DR flag in FLSR