Datasheet

Rev. 2.00 Aug. 20, 2008 Page 1181 of 1198
REJ09B0403-0200
Item Page Revision (See Manual for Details)
Section 19 LPC
Interface (LPC)
19.3.1 Host Interface
Control Registers 0 and
1 (HICR0 and HICR1)
• HICR1
678 Amended
Bit Bit Name Description
0 LSCIB LSCI output Bit
Controls LSCI output in combination with the
LSCIE bit. For details, refer to description on the
LSCIE bit in HICR0.
Figure 19.11 Clock Start
Request Timing
749 Amended
LCLK
CLKRUN
Pull-up enable
Driven by the host processor
Driven by the slave processor
1 2 3 4 5 6
Table 19.14 Host
Address Example
755 Amended
Register Host Address
when LADR3 = H'A24F
Host Address
when LADR3 = H'3FD0
Section 20 Ethernet
Controller (EtherC)
Table 20.1
Pin Configuration
759 Amended and added
Type Abbreviation I/O Function
PHY register
interface
signals
MDC Output Management Data Clock
Reference clock signal for
information transfer via MDIO
Others EXOUT Output External Output
Figure 20.10 1-Bit Data
Read Flowchart
784 Modified
(1) Write to PHY interface register
MMD = 0
MDC = 1
(2) Write to PHY
interface register read
MMD = 0
MMC = 1
MDI is read data