Datasheet

Rev. 2.00 Aug. 20, 2008 Page 1182 of 1198
REJ09B0403-0200
Item Page Revision (See Manual for Details)
Section 21 Ethernet
Controller Direct
Memory Access
Controller (E-DMAC)
21.2.8 Transmit/Receive
Status Copy Enable
Register (TRSCER)
806 Amended
TRSCER specifies whether or not transmit and
receive status
information reported by bits 7 and 4 in the EtherC/E-DMAC
status register is to be indicated in bit RFE in the corresponding
descriptor. Bits in this register correspond to bits 7 and 4 in the
EtherC/E-DMAC status register (EESR). When a bit is cleared
to 0, the transmit status (bits 11 to 8 in EESR) is indicated in bits
TFS3 to TFS0 in the transmit descriptor, and the receive status
(bits 7 and 4 in EESR) is indicated in bit RFE of the receive
descriptor. When a bit is set to 1, the occurrence of the
corresponding interrupt is not indicated in the descriptor. After
this LSI is reset, all bits are cleared to 0.
Bit Bit Name
Initial
value
R/W Description
31 to 8  All 0 R Reserved
These bits are always read as 0. The
initial value should not be changed.
7 RMAFCE 0 R/W RMAF Bit Copy Directive
0: Indicates the RMAF bit state in bit
RFE of the receive descriptor
1: Occurrence of the corresponding
interrupt is not indicated in bit RFE of
the receive descriptor
6, 5  All 0 R Reserved
These bits are always read as 0. The
initial value should not be changed.
4 RRFCE 0 R/W RRF Bit Copy Directive
0: Indicates the RRF bit state in bit RFE
of the receive descriptor
1: Occurrence of the corresponding
interrupt is not indicated in bit RFE of
the receive descriptor
3 to 0  All 0 R Reserved
These bits are always read as 0. The
initial value should not be changed.