Datasheet

Rev. 2.00 Aug. 20, 2008 Page 1186 of 1198
REJ09B0403-0200
Item Page Revision (See Manual for Details)
Section 26 Boundary
Scan (JTAG)
Table 26.1 Pin
Configuration
1019 Deleted
Pin Name Function
Test clock Test clock inputProvides an independent clock
supply to the JTAG. As the clock input to the
ETCK pin is supplied directly to the JTAG, a
clock waveform with a duty cycle close to 50%
should be input. For details, see section 31,
Electrical Characteristics. If there is no input, the
ETCK pin is fixed to 1 by an internal pull
Test mode select Test mode select input Sampled on the rise of
the ETCK pin. The ETMS pin controls the
internal state of the TAP controller. If there is no
input, the ETMS pin is fixed to 1 by an internal
pull
Test data input Serial data inputPerforms serial input of
instructions and data for JTAG registers. ETDI is
sampled on the rise of the ETCK pin. If there is
no input, the ETDI pin is fixed to 1 by an internal
pull
Test data output Serial data outputPerforms serial output of
instructions and data from JTAG registers.
Transfer is performed in synchronization with the
ETCK pin. If there is no output, the ETDO pin
goes to the high
Test reset Test reset input signalInitializes the JTAG
asynchronously. If there is no input, the ETRST
pin is fixed to 1 by an internal pull
Table 26.3
Correspondence
between Pins and
Boundary Scan Register
(H8S/2472 Group)
1025,
1029
Amended
Pin No. Pin Name Input/Output Bit No.
Input 231
Enable 230
R6 P82
Output
229
Input
108
Enable 107
D13 P17
Output 106