Datasheet

Rev. 2.00 Aug. 20, 2008 Page 1187 of 1198
REJ09B0403-0200
Item Page Revision (See Manual for Details)
1031 Description added
Though the pin no. for the H8S/2462 Group and the H8S/2463
Group differs, the bit no. for these products is the same. The
following table is listed with the pin no. of the H8S/2462 Group.
Table 26.4
Correspondence
between Pins and
Boundary Scan Register
(H8S/2462 Group and
H8S/2463 Group)
1033 Amended
Pin No. Pin Name Input/Output Bit No.
Input
251
Enable 252
35 PA5
Output
249
—
—
— —
36 VCC
—
—
26.6 Usage Notes 1045 Deleted
1. A reset must always be executed by driving the ETRST pin to
0, regardless of whether or not the JTAG is to be activated. …
If the JTAG is not to be activated, drive the ETRST, ETCK,
ETMS, and ETDI pins to 1 or the high-impedance state.
These pins are internally pulled up and are noted in standby
mode.
Section 28 Power-Down
Modes
28.1.4 Sub-Chip Module
Stop Control Registers
BH, BL (SUBMSTPBH,
SUBMSTPBL)
1062 Amended
• SUBMSTPBL
Bit Name Corresponding Module
SMSTPB4 PECI
This bit is not incorporated in the H8S/2463 Group.
The initial values should not be changed.
Section 29 List of
Registers
29.1 Register
Addresses (Address
Order)
1085 Added
Notes: 1. The registers related to USB are supported only by
the H8S/2472 Group.
2. The registers related to PECI are supported only by
the H8S/2472 Group and the H8S/2462 Group.