Datasheet

Section 5 Interrupt Controller
Rev. 2.00 Aug. 20, 2008 Page 87 of 1198
REJ09B0403-0200
5.3.6 IRQ Status Registers (ISR16, ISR)
The ISR registers are flag registers that indicate the status of IRQ15 to IRQ0 interrupt requests.
• ISR16
Bit Bit Name
Initial
Value
R/W Description
7 to 0 IRQ15F to
IRQ8F
All 0 R/W [Setting condition]
• When the interrupt source selected by the ISCR16
registers occurs
[Clearing conditions]
• When reading 1, then writing 0
• When interrupt exception handling is executed when
low-level detection is set and IRQn* or ExIRQn input is
high
• When IRQn interrupt exception handling is executed
when falling-edge, rising-edge, or both-edge detection
is set
(n = 15 to 8)
Note: * IRQn stands for IRQ15 to IRQ8.
• ISR
Bit Bit Name
Initial
Value
R/W Description
7 to 0 IRQ7F to
IRQ0F
All 0 R/W [Setting condition]
• When the interrupt source selected by the ISCR
registers occurs
[Clearing conditions]
• When reading 1, then writing 0
• When interrupt exception handling is executed when
low-level detection is set and IRQn* or ExIRQn input is
high
• When IRQn interrupt exception handling is executed
when falling-edge, rising-edge, or both-edge detection
is set
(n = 7 to 0)
Note: * IRQn stands for IRQ7 to IRQ0.