Datasheet

Section 5 Interrupt Controller
Rev. 2.00 Aug. 20, 2008 Page 96 of 1198
REJ09B0403-0200
7. The CPU generates a vector address for the accepted interrupt and starts execution of the
interrupt handling routine at the address indicated by the contents of the vector address in the
vector table.
Program execution state
Interrupt generated?
NMI
An interrupt with interrupt
control level 1?
IRQ0
IRQ1
EINT
IRQ0
IRQ1
EINT
I = 0
Save PC and CCR
I 1
Read vector address
Branch to interrupt handling routine
Yes
No
Yes
Yes
Yes
No
No
Yes
No
Yes No
Yes
Yes
No
No
Yes
Yes
No
Pending
Figure 5.4 Flowchart of Procedure up to Interrupt Acceptance in Interrupt Control Mode 0