Datasheet

Section 6 Bus Controller (BSC)
Rev. 2.00 Aug. 20, 2008 Page 110 of 1198
REJ09B0403-0200
6.2 Input/Output Pins
Table 6.1 summarizes the pin configuration of the bus controller.
Table 6.1 Pin Configuration
Symbol I/O Function
AS Output Strobe signal indicating that address output on the address
bus is enabled (when the IOSE bit in SYSCR is cleared to 0).
Note that this signal is not output when the 256-Kbyte
extended area is accessed (the CS256E bit in SYSCR is 1).
IOS Output Chip select signal indicating that the IOS extended area is
being accessed (when the IOSE bit in SYSCR is 1).
CS256 Output Chip select signal indicating that the 256-Kbyte extended
area is being accessed (when the CS256E bit in SYSCR is
1).
RD Output Strobe signal indicating that the external address space is
being read.
HWR Output Strobe signal indicating that the external address space is
being written to, and the upper half (D15 to D8, AD15 to
AD8) of the data bus is valid.
LWR Output Strobe signal indicating that the external address space is
being written to, and the lower half (D7 to D0, AD7 to AD0) of
the data bus is valid.
WAIT Input Wait request signal when accessing the external space.
WR Output Strobe signal indicating that the external address space is
being written to.
HBE Output Strobe signal indicating that the external address space is
being accessed, and the upper half (D15 to D8) of the data
bus is valid.
LBE Output Strobe signal indicating that the external address space is
being accessed, and the lower half (D7 to D0) of the data
bus is valid.
AH Output Signal indicating address fetch timing when the bus is in
address-data multiplex bus state.
AD15 to AD0 Input/Output Address output and data input/output pins for address-data
multiplex extension.