Datasheet

Section 6 Bus Controller (BSC)
Rev. 2.00 Aug. 20, 2008 Page 113 of 1198
REJ09B0403-0200
6.3.2 Bus Control Register 2 (BCR2)
BCR2 is used to specify the access mode for the extended area.
Bit Bit Name
Initial
Value
R/W Description
7, 6  All 0 R/W Reserved
The initial value should not be changed.
5, 4  All 1 R/W Reserved
The initial value should not be changed.
3 ADFULLE 0 R/W Address Output Full Enable
Controls the address output, A23 to A21, in access to the
extended area. See section 8, I/O Ports. This is not
supported while ADMXE = 1.
2 EXCKS 0 R/W External Extension Clock Select
Selects the operating clock used in external extended
area access.
0: Medium-speed clock is selected as the operating clock
1: System clock (φ) is selected as the operating clock.
The operating clock is switched in the bus cycle prior to
external extended area access.
1  1 R/W Reserved
The initial value should not be changed.
0  0 R/W Reserved
The initial value should not be changed.