Datasheet

Rev. 2.00 Aug. 20, 2008 Page xv of xlviii
11.2.1 Timer Counter (TCNT)......................................................................................... 396
11.2.2 Time Constant Register A (TCORA).................................................................... 397
11.2.3 Time Constant Register B (TCORB) .................................................................... 397
11.2.4 Timer Control Register (TCR).............................................................................. 398
11.2.5 Timer Control/Status Register (TCSR)................................................................. 401
11.2.6 Timer Connection Register S (TCONRS)............................................................. 405
11.3 Operation Timing............................................................................................................... 406
11.3.1 TCNT Count Timing............................................................................................. 406
11.3.2 Timing of CMFA and CMFB Setting at Compare-Match .................................... 406
11.3.3 Timing of Counter Clear at Compare-Match........................................................ 407
11.3.4 Timing of Overflow Flag (OVF) Setting .............................................................. 407
11.4 TMR_0 and TMR_1 Cascaded Connection....................................................................... 408
11.4.1 16-Bit Count Mode ............................................................................................... 408
11.4.2 Compare-Match Count Mode ............................................................................... 408
11.5 Interrupt Sources................................................................................................................ 409
11.6 Usage Notes ....................................................................................................................... 410
11.6.1 Conflict between TCNT Write and Counter Clear................................................ 410
11.6.2 Conflict between TCNT Write and Increment...................................................... 411
11.6.3 Conflict between TCOR Write and Compare-Match............................................ 412
11.6.4 Switching of Internal Clocks and TCNT Operation.............................................. 413
11.6.5 Mode Setting with Cascaded Connection ............................................................. 414
Section 12 Watchdog Timer (WDT)..................................................................415
12.1 Features.............................................................................................................................. 415
12.2 Input/Output Pins............................................................................................................... 417
12.3 Register Descriptions ......................................................................................................... 417
12.3.1 Timer Counter (TCNT)......................................................................................... 417
12.3.2 Timer Control/Status Register (TCSR)................................................................. 418
12.4 Operation ........................................................................................................................... 422
12.4.1 Watchdog Timer Mode......................................................................................... 422
12.4.2 Interval Timer Mode............................................................................................. 424
12.4.3 RESO Signal Output Timing ................................................................................ 425
12.5 Interrupt Sources................................................................................................................ 426
12.6 Usage Notes ....................................................................................................................... 427
12.6.1 Notes on Register Access...................................................................................... 427
12.6.2 Conflict between Timer Counter (TCNT) Write and Increment........................... 428
12.6.3 Changing Values of CKS2 to CKS0 Bits.............................................................. 428
12.6.4 Changing Value of PSS Bit................................................................................... 428
12.6.5 Switching between Watchdog Timer Mode and Interval Timer Mode................. 429
12.6.6 System Reset by RESO Signal.............................................................................. 429