Datasheet

Section 6 Bus Controller (BSC)
Rev. 2.00 Aug. 20, 2008 Page 132 of 1198
REJ09B0403-0200
(2) 8-Bit, 3-State Access Space
Figure 6.6 shows the bus timing for an 8-bit, 3-state access space. When an 8-bit access space is
accessed, the upper half (D15 to D8) of the data bus is used. Wait states can be inserted.
Bus cycle
T
1
T
2
Address bus
φ
AS
(IOSE = 0)
RD
D15 to D8
Valid
D7 to D0
Invalid
Read
HWR
D15 to D8
Valid
Write
T
3
IOS
(IOSE = 1)
CS256
(CS256E = 1)
Note:
*
* For external address space access, this signal is not output when the 256-Kbyte extended area
is accessed with CS256E = 1.
Figure 6.6 Bus Timing for 8-Bit, 3-State Access Space