Datasheet

Section 6 Bus Controller (BSC)
Rev. 2.00 Aug. 20, 2008 Page 136 of 1198
REJ09B0403-0200
(4) 16-Bit, 3-State Access Space
Figures 6.10 to 6.12 show bus timings for a 16-bit, 3-state access space. When a 16-bit access
space is accessed, the upper half (D15 to D8) of the data bus is used for even addresses, and the
lower half (D7 to D0) for odd addresses. Wait states can be inserted.
Bus cycle
T
1
T
2
Address bus
φ
AS (IOSE = 0)
RD
D15 to D8
Valid
D7 to D0
Invalid
Read
*
HWR
LWR
D15 to D8
Valid
D7 to D0
Undefined
Write
High level
T
3
IOS (IOSE = 1)
CS256 (CS256E = 1)
Note: * For external address space access, this signal is not output when the 256-Kbyte extended area
is accessed with CS256E = 1.
Figure 6.10 Bus Timing for 16-Bit, 3-State Access Space (Even Byte Access)