Datasheet

Section 6 Bus Controller (BSC)
Rev. 2.00 Aug. 20, 2008 Page 142 of 1198
REJ09B0403-0200
6.5.5 Basic Operation Timing in Address-Data Multiplex Extended Mode
(1) 8-Bit, 2-State Data Access Space
Figures 6.16 and 6.17 show the bus timing for an 8-bit, 2-state access space. When an 8-bit access
space is accessed, the lower half (AD7 to AD0) of the data bus is used. Wait states cannot be
inserted.
Read Cycle
Address Data
Data
Address Data
Write Cycle
T
1
T
2
T
3
T
AW
T
4
T
1
T
2
T
3
T
AW
T
4
φ
CS256
IOS
AH
RD
HWR
AD7 to AD0
Address Address
Data
Figure 6.16 Bus Timing for 8-Bit, 2-State Access Space