Datasheet

Section 6 Bus Controller (BSC)
Rev. 2.00 Aug. 20, 2008 Page 145 of 1198
REJ09B0403-0200
Read Cycle
Address
Data Address Data
Write Cycle
T
1
T
2
T
3
T
4
T
1
T
2
T
3
T
4
CS256
IOS
AH
RD
HWR
LWR
AD15 to AD8
AD7 to AD0
φ
Address Address
Data Data
Address Address
Figure 6.20 Bus Timing for 16-Bit, 2-State Access Space (2) (Even Byte Access)
Read Cycle
Address Data Data
Write Cycle
T
1
T
2
T
3
T
AW
T
4
Address
T
1
T
2
T
3
T
AW
T
4
CS256
IOS
AH
RD
HWR
LWR
AD15 to AD8
AD7 to AD0
φ
Address Address
Data Data
Address Address
Figure 6.21 Bus Timing for 16-Bit, 2-State Access Space (3) (Odd Byte Access)