Datasheet

Section 6 Bus Controller (BSC)
Rev. 2.00 Aug. 20, 2008 Page 151 of 1198
REJ09B0403-0200
By program wait
T
1
Address bus
φ
AS (IOSE = 0)
RD
Data bus
Read data
Read
*
IOS (IOSE = 1)
WR
Write data
Write
Note: ↓ shown in φ clock indicates the WAIT pin sampling timing.
WAIT
Data bus
T
2
T
W
T
W
T
W
T
3
By WAIT pin
* For external address space access, this signal is not output when the 256-kbyte extended area
is accessed with CS256E = 1.
Figure 6.28 Example of Wait State Insertion Timing (Pin Wait Mode)