Datasheet

Section 6 Bus Controller (BSC)
Rev. 2.00 Aug. 20, 2008 Page 152 of 1198
REJ09B0403-0200
(2) In Address-Data Multiplex Extended Mode
(a) Program Wait Mode
Program wait mode includes address wait and data wait.
• 256-Kbyte extended area and IOS extended area
Zero or one state of address wait T
AW
is inserted between T
1
and T
2
states. Zero to three states
of data wait T
DSW
is inserted between T
4
and T
5
states.
(b) Pin Wait Mode
When accessing the external address space, a specified number of wait states T
DSW
can be inserted
between the T
4
state and T
5
state of data state. The number of wait states T
DSW
is specified by the
settings of the WC1 and WC0 bits. If the WAIT pin is low at the falling edge of φ in the last T
4
,
T
DSW
, or T
DOW
state, another T
DOW
state is inserted. If the WAIT pin is held low, T
DOW
states are
inserted until it goes high.
Pin wait mode is useful when inserting four or more T
DOW
states, or when changing the number of
T
DOW
states to be inserted for each external device.
(c) Pin Auto-Wait Mode
A specified number of wait states T
DOW
are inserted between the T
4
state and T
5
state when
accessing the external address space if the WAIT pin is low at the falling edge of φ in the last T
4
state. The number of wait states T
DOW
is specified by the settings of the WC1 and WC0 bits. Even
if the WAIT pin is held low, T
DOW
states are inserted only up to the specified number of states.
Pin auto-wait mode enables the low-speed memory interface only by inputting the chip select
signal to the WAIT pin.
Figure 6.29 shows an example of wait state insertion timing in pin wait mode.