Datasheet

Rev. 2.00 Aug. 20, 2008 Page xix of xlviii
17.3.7 SS Transmit Data Registers 0 to 3 (SSTDR0 to SSTDR3)................................... 564
17.3.8 SS Receive Data Registers 0 to 3 (SSRDR0 to SSRDR3).................................... 565
17.3.9 SS Shift Register (SSTRSR)................................................................................. 565
17.4 Operation ........................................................................................................................... 566
17.4.1 Transfer Clock ...................................................................................................... 566
17.4.2 Relationship of Clock Phase, Polarity, and Data .................................................. 566
17.4.3 Relationship between Data Input/Output Pins and Shift Register ........................ 567
17.4.4 Communication Modes and Pin Functions ........................................................... 568
17.4.5 SSU Mode............................................................................................................. 570
17.4.6 SCS Pin Control and Conflict Error...................................................................... 578
17.4.7 Clock Synchronous Communication Mode .......................................................... 579
17.5 Interrupt Requests .............................................................................................................. 585
17.6 Usage Note......................................................................................................................... 585
17.6.1 Setting of Module Stop Mode............................................................................... 585
Section 18 I
2
C Bus Interface (IIC) .....................................................................587
18.1 Features.............................................................................................................................. 587
18.2 Input/Output Pins............................................................................................................... 590
18.3 Register Descriptions ......................................................................................................... 591
18.3.1 I
2
C Bus Data Register (ICDR) .............................................................................. 591
18.3.2 Slave Address Register (SAR).............................................................................. 592
18.3.3 Second Slave Address Register (SARX) .............................................................. 593
18.3.4 I
2
C Bus Mode Register (ICMR)............................................................................ 595
18.3.5 I
2
C Bus Transfer Rate Select Register (IICX3)..................................................... 597
18.3.6 I
2
C Bus Control Register (ICCR).......................................................................... 600
18.3.7 I
2
C Bus Status Register (ICSR)............................................................................. 609
18.3.8 I
2
C Bus Extended Control Register (ICXR).......................................................... 613
18.3.9 I
2
C SMBus Control Register (ICSMBCR)............................................................ 617
18.4 Operation ........................................................................................................................... 619
18.4.1 I
2
C Bus Data Format ............................................................................................. 619
18.4.2 Initialization .......................................................................................................... 621
18.4.3 Master Transmit Operation ................................................................................... 621
18.4.4 Master Receive Operation..................................................................................... 625
18.4.5 Slave Receive Operation....................................................................................... 634
18.4.6 Slave Transmit Operation ..................................................................................... 642
18.4.7 IRIC Setting Timing and SCL Control ................................................................. 645
18.4.8 Operation Using the DTC ..................................................................................... 648
18.4.9 Noise Canceler...................................................................................................... 650
18.4.10 Initialization of Internal State ............................................................................... 650
18.5 Interrupt Source ................................................................................................................. 652