Datasheet

Section 7 Data Transfer Controller (DTC)
Rev. 2.00 Aug. 20, 2008 Page 162 of 1198
REJ09B0403-0200
Internal address bus
DTCER
A
to
DTCERF
DTVECR
Interrupt controller DTC On-chip RAM
Internal data bus
CPU interrupt
request
MRA MRB
CRA CRB
DAR
SAR
Interrupt
request
MRA, MRB:
CRA, CRB:
SAR:
DAR:
DTCERA to DTCERF:
DTVECR:
DTC mode register A, B
DTC transfer count register A, B
DTC source address register
DTC destination address register
DTC enable registers A to F
DTC vector register
[Legend]
DTC activation request
Control logic
Register information
Figure 7.1 Block Diagram of DTC