Datasheet

Section 7 Data Transfer Controller (DTC)
Rev. 2.00 Aug. 20, 2008 Page 167 of 1198
REJ09B0403-0200
Table 7.1 Correspondence between Interrupt Sources and DTCER
Register
Bit Bit Name DTCERA DTCERB DTCERC DTCERD DTCERE DTCERF*
7 DTCEn7 (16)IRQ0   (86)TXI1  (115)USBINT0
6 DTCEn6 (17)IRQ1 (76)IICI2  (89)RXIS  (118)USBINT1
5 DTCEn5 (18)IRQ2 (94)IICI0  (90)TXIS  
4 DTCEn4 (19)IRQ3  (29)EVENTI (78)IICI3  
3 DTCEn3 (28)ADI   (98)IICI1 (104)ERR1 
2 DTCEn2   (81)RXI3  (105)IBFI1 
1 DTCEn1   (82)TXI3  (106)IBFI2 
0 DTCEn0   (85)RXI1  (107)IBFI3 
[Legend]
n: A to F
( ): Vector number
: Reserved. The write value should always be 0.
*: Only in the H8S/2472
7.2.8 DTC Vector Register (DTVECR)
DTVECR enables or disables DTC activation by software, and sets a vector number for the
software activation interrupt.
Bit Bit Name
Initial
Value
R/W Description
7 SWDTE 0 R/W DTC Software Activation Enable
Setting this bit to 1 activates DTC. Only 1 can be written to
this bit.
[Clearing conditions]
• When the DISEL bit is 0 and the specified number of
transfers have not ended
• When 0 is written to the DISEL bit after a software-
activated data transfer end interrupt (SWDTEND)
request has been sent to the CPU.
This bit will not be cleared when the DISEL bit is 1 and
data transfer has ended or when the specified number of
transfers has ended.