Datasheet

Section 7 Data Transfer Controller (DTC)
Rev. 2.00 Aug. 20, 2008 Page 184 of 1198
REJ09B0403-0200
7.6.7 Number of DTC Execution States
Table 7.8 lists the execution status for a single DTC data transfer, and table 7.9 shows the number
of states required for each execution status.
Table 7.8 DTC Execution Status
Mode
Vector Read
I
Register
Information
Read/Write
J
Data Read
K
Data Write
L
Internal
Operations
M
Normal 1 6 1 1 3
Repeat 1 6 1 1 3
Block transfer 1 6 N N 3
[Legend]
N: Block size (initial setting of CRAH and CRAL)
Table 7.9 Number of States Required for Each Execution Status
Object to be Accessed
On-Chip RAM
(H'FFEC00 to
H'FFEFFF)
On-Chip RAM
(On-chip RAM area
other than H'FFEC00 to
H'FFEFFF)
On-
Chip
ROM
On-Chip
I/O
Registers
External Devices
Bus width 32 16 16 8 16 8 8 16 16
Access states 1 1 1 2 2 2 3 2 3
Vector read S
I
— — 1 — — 4 6 + 2m 2 3 + m Execution
status
Register
information
read/write S
J
1 — — — — — — — —
Byte data read S
K
1 1 1 2 2 2 3 + m 2 3 + m
Word data read
S
K
1 1 1 4 2 4 6 + 2m 2 3 + m
Byte data write S
L
1 1 1 2 2 2 3 + m 2 3 + m
Word data write
S
L
1 1 1 4 2 4 6 + 2m 2 3 + m
Internal operation
S
M
1 1 1 1 1 1 1 1 1