Datasheet

Section 8 I/O Ports
Rev. 2.00 Aug. 20, 2008 Page 205 of 1198
REJ09B0403-0200
(6) Noise Canceler Cycle Setting Register (NCCS)
NCCS controls the sampling cycle of the noise cancelers.
Bit Bit Name Initial Value R/W Description
7 to 3  Undefined R/W Reserved
Undefined value is read from these bits.
2
1
0
NCCK2
NCCK1
NCCK0
0
0
0
R/W
R/W
R/W
These bits set the sampling cycle of the noise cancelers.
• When φ = 34 MHz
000: 0.06 µs φ/2 100: 963.8 µs φ/32768
001: 0.94 µs φ/32 101: 1.9 ms φ/65536
010: 15.1 µs φ/512 110: 3.9 ms φ/131072
011: 240.9 µs φ/8192 111: 7.7 ms φ/262144
Latch
∆t
∆t
Sampling clock selection
φ/2, φ/32, φ/512, φ/8192,
φ/32768, φ/65536,
φ/131072, φ/262144
Pin input
Sampling clock
Match
detection
circuit
Port data
register
Latch
Latch
Figure 8.1 Noise Canceler Circuit